Parallel In Parallel Out (PIPO) shift registers are the type of storage devices in which both data loading as well as data retrieval processes occur in parallel mode. Figure 1 shows a PIPO register capable of storing n-bit input data word (Data in). Here each flip-flop stores an individual bit of the data in appearing as its input (FF 1 stores B 1 appearing at D 1; FF 2 stores B 2 appearing at D 2 FF n stores B n appearing at D n) at the instant of first clock pulse. Further, at the same instant, the bit stored in each individual also appears at their respective output pins (Q 1 = D 1; Q 2 = D 2 Q n = B n). This indicates that both data storage as well as data recovery occur at a single (and at the same) clock pulse in PIPO registers. However one has to note that the PIPO register shown in Figure 1 is not capable of shifting the data bits. In order to convert PIPO register of Figure 1 into PIPO shift register, one has to modify its circuit by adding combinational circuit and control line as shown by Figure 2.
The 74HC164 Shift Register and Your Arduino: Shift registers are a very important part of digital logic, they act as glue in between the parallel and serial worlds. They reduce wire counts, pin use and even help take load off of your cpu by being able to store their data.They come in differe.
Here if line goes low, A 2 AND gates of all the combinational circuits become active while A 1 gates become inactive. Thus the bits of the input data word (Data in) appearing as inputs to the gates A 2 are passed on as the outputs which are further loaded/stored into respective flip-flops at the appearance of first leading edge of the clock (except the bit B 1 which gets directly stored into FF 1 at the first clock tick). This indicates that all the bits of the input data word are stored into the register components at the same clock tick. At the same time, these bits also appear at the output pins of the respective flip-flops thus yielding parallel-output data word at the same clock tick. Further when line is made high, A 1 gates of all the combinational circuits enable while A 2 gates get disabled.
This causes the output bit of each flip-flop to appear at the output of the OR gate driving the very-next flip-flop (except the last flip-flop FF n) i.e. Output bit of FF 1 (Q 1) appears as the output of 1 (O 1) connected to D 2; Q 2 = output of O 2 = D 3 and so on. At this stage, if the rising edge of the clock pulse appears, then Q 1 appears at Q 2, Q 2 appears at Q 3, and Q n-1 appears at Q n. This is nothing but right-shift of the data stored within the register by one-bit. This working is further emphasized in the Table I and Figure 3. Similar to the right-shift PIPO shift register, there can also be a left-shift PIPO shift register as shown by Figure 4. Nevertheless the mode of working remains the same.